Abstract: Since few years, Artificial Neural Networks are heavily used in Computer Vision and Natural Language Processing domain in order to create intelligent applications for smart systems. It has also become an important area of research in Artificial Intelligence. Artificial Neural Networks perform well with specialized accelerated software Frameworks on higher computational resources (e.g GPU) in less constrained environments. But advances in VLSI technology and availability of compact SoC and embedded devices with limited computational resources and less memory limits the use of Multilayer Neural Networks called Deep Neural Networks on low power embedded hardware. Due to the fact that Deep Neural Networks and especially Convolutional Neural Networks are power and computation resource hungry mathematical computations, the new research is developed on optimization of Deep Neural Networks for its efficient inference under limited resource environments without significant loss in its performance. This thesis aims at the research of compression and optimization strategy of Deep Neural Networks that can run efficiently on embedded hardware with more generalized processing techniques. The constraints, requirements and statistical analysis of neural network computation which plays key role in identifying the important facets of compressed neural networks has been presented in this work. Deployability and inference time of Deep Neural Networks on embedded hardware such as smart mobile phones, Raspberry-pi and other FPGAs is fairly important for fast and real time processing for vision based applications. The implementation, evaluation results and analysis of computation time and classification accuracy of standard and newly designed deep neural network architectures has been demonstrated in this work for standard object classification tasks on embedded hardware.